1. Technical Field
The present invention relates generally to computer-aided design of photolithographic masks used in the manufacturing of integrated circuits. More specifically, the present invention is directed to an improved method, computer program product, and apparatus for performing optical proximity correction in such masks.
2. Description of the Related Art
Integrated circuits (ICs) are commonly manufactured through a photolithographic process. In photolithography, a layer of light-sensitive material (photoresist) is applied atop a layer of material to be etched by the process. A geometric pattern is applied to the photoresist by shining light of a prescribed wavelength through a photolithographic mask (also referred to as a “photomask” or, simply, “mask”) containing the pattern. A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. (Henceforth herein, the term “region of transparency” shall be used to denote either a hole in the plate or an actual transparent portion of the plate, so that a single term may be used to refer to either possibility. A “region of opacity” shall be used to denote an opaque feature in the photomask. The term “region” shall be used to denote either a region of transparency or a region of opacity.) In practice, lithographic photomasks are typically transparent fused silica blanks covered with a pattern defined with a chrome metal absorbing film. They are typically manufactured to a size that is substantially larger than that of the circuit itself, and reduction optics are used to project the mask pattern onto the photoresist at the correct size. The light passing through the mask causes changes to occur in the photoresist such that a subsequent etching process leaves selected portions of the photoresist and immediately underlying material layer intact, while removing undesired portions of such layers. For example, photolithography can be used to define the geometric pattern of the polysilicon layer in a MOS (metal-oxide semiconductor) integrated circuit technology (the layer in which the gates of MOSFETs [metal-oxide semiconductor field-effect transistors] are defined).
FIG. 1, for example, depicts the IC layout of a simple MOSFET 100. MOSFET 100 is made up of a region of doped silicon 102 (either N-type or P-type) overlapped by a region of polysilicon material 104. The gate of the transistor is defined by the rectangular portion (106) of polysilicon region 104 that overlaps doped silicon region 102. In the standard Shichman-Hodges MOSFET model, the electrical behavior of the MOSFET thus constructed is modeled by a parameter “K,” which is directly proportional to the ratio of the width (108) of gate 106 to its length (110). Thus, the relative dimensions of transistor features are critical to the proper electrical behavior of a given device.
The minimum feature sizes available in a given technology are limited, at least in part, by the nature of the photolithographic process itself. Specifically, as feature sizes approach the wavelengths of light used in the process (e.g., at sub-micron feature sizes for conventional photolithography using ultraviolet light), diffraction (a result of the wave-nature of electromagnetic radiation) reduces the fidelity of the image projected onto the photoresist. For example, a rectilinear feature 200 in a photomask (existing either as a region of transparency or as a region of opacity), as depicted in FIG. 2, might be rendered in a distorted curvilinear shape (such as shape 300) in the photoresist, as depicted in FIG. 3.
One potential way of dealing with this problem is to shorten the wavelengths of light used. Thus, the use of extremely short-wavelength ultraviolet radiation or X-ray radiation for photolithography is a topic of current research. Another method of dealing with this problem is to employ what has come to be known as optical proximity correction (OPC). In OPC, diffusion-induced distortions in the pattern applied to the photoresist are reduced in severity by introducing small irregularities into the mask itself. The effect of these irregularities is to “predistort” the mask pattern in such a way that the diffraction-induced distortions are minimized. For example, in FIG. 4, an OPC-modified version 400 of mask pattern 200 is depicted, wherein irregularities (e.g., irregularities 402 and 404) are introduced into the mask shape so as to counteract the distortions caused by diffraction. OPC, as it is practiced in the art, relies on computerized optimization algorithms to minimize “edge placement error” (EPE). EPE is a metric that represents the distance between a location on the projected image and a corresponding location in the mask pattern. In a typical implementation, modifications to the mask pattern are made using a gradient-descent approach to minimize the overall EPE of a mask pattern.
Although EPE-based OPC is a useful technique, the results obtained from such technique are not necessarily optimal in the sense of electrical behavior. More specifically, although the projected image may better conform to the desired shape, the electrical behavior of the resulting device may differ substantially from what is desired, thus necessitating complex electrical simulation and further adjustment of the mask pattern in response.
What is needed, therefore, is a method of performing optical proximity correction which respects the electrical properties of the device being manufactured. The present invention provides a solution to this and other problems, and offers other advantages over previous solutions.